1. Field of the Invention
The present invention relates to techniques for testing semiconductor chips. More specifically, the present invention relates to a method and apparatus for generating tests for transition-fault testing of semiconductor chips.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, onto a single semiconductor chip. These advances also allow a semiconductor chip to operate at higher clock frequencies. Unfortunately, these advances are also making it more difficult to meet timing constraints because of the shorter clock cycle times and longer wire delays. Although a semiconductor chip may meet timing constraints during the design phase, a manufactured semiconductor chip may contain defects, due to process variations, which cause the chip to fail. Hence, prior to shipping semiconductor chips to customers, the semiconductor chips are tested to separate defective chips from non-defective chips.
Present semiconductor testing techniques typically utilize stuck-at fault testing, which generates test vectors and expected test values based on the assumption that a net within the semiconductor chip is stuck at either the power supply or at ground. Although CMOS circuits are not well represented by stuck-at faults, stuck-at fault testing has been effective in ensuring that the physical structure of the semiconductor chip is covered by the resulting test set. Unfortunately, timing-related defects, such as path delay faults and transition faults, remain uncovered.
For typical semiconductor chip designs, generating test patterns to detect path delay faults is intractable because of the large number of paths that need to be covered. Thus, transition fault testing is the only tractable solution available to detect timing failures.
Automatic test pattern generation (ATPG) techniques obtain their efficiency by targeting the easiest solutions first. For transition faults, this means that the transition faults are detected along shorter paths (i.e. the paths with a larger slack time). Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. Fault simulation adds to the efficiency of the test generation process by taking credit for transition faults that are randomly detected by the tests generated for the targeted fault. These transition faults are usually detected along paths with slacks that are random with respect to all the paths on which the transition faults can be detected.
Transition fault tests catch timing failures that exceed the timing of the test. FIG. 1 illustrates the timing of paths along which a transition fault can be tested. In FIG. 1, a test is applied at t=0 to expose timing failures and is measured one clock period later (at TMC). In this case, TTEST and TMC are the same. Note that TMC is the machine cycle time (i.e. the clock speed at which the semiconductor chip operates at during normal operation) and TTEST is the time when the test measurement is made. In this example, Path A, represents a test for a transition fault along its longest path (i.e. a path with the minimum slack). Path B represents a test for the same transition fault along a shorter path (i.e. a path with a larger slack time). The smallest timing defect that can be detected by a test is equal to the slack of the path on which the fault was tested. Since the slack along Path A (SLP) is less than the slack along Path B (SSP), the test along Path A is better than the test along Path B for detecting small-delay timing defects.
Since test generation is an NP-Complete problem and heuristics are used to guide the test generator to the quickest solution, Path B is only one of the short paths of the many possible short paths that exist for the targeted transition fault. A typical ATPG tool produces a path similar to Path B (i.e. a shorter path).
The relationship between slack and the defect level is quantified in the following equation:DL=1−Y(1−SDFC) The defect level (DL) is a function of the yield Y and statistical delay fault coverage (SDFC), which represents the defect coverage equivalent for the path length along which the test occurs. A fault detected along the shorter path contributes approximately (TMC−SSP)/(TMC−SLP) towards SDFC which is the average over all the faults/defects in the design.
Two techniques are used to generate test patterns for detecting transition faults:
1. Binning
2. Long path ATPG
Binning brings the test time (TTEST) closer to the shorter path which was generated by the ATPG tool, thereby reducing the slack for this shorter path. In contrast, long path ATPG selects the path closer to the TMC.
Unfortunately, bringing in TTEST tighter than the machine time (TMC) to get better quality transition fault tests causes problems for which there are no solutions. When TTEST is brought in relative to TMC, all flip-flops that do not meet the new timing need to be masked to ignore the value captured in them. While this is possible for a good machine (i.e. non-defective chip), it is an intractable problem for a faulty machine (i.e. defective chip). The masking of the flip-flops that do not meet the new timing accounts for signals propagating along the longest path, which cannot reach the destination flip-flops within the shortened test time (TTEST<TMC). In a system where the clock cycle time is TMC, these flip-flops receive the correct values (assuming that there are no defects). If these flip-flops are not masked during testing, the semiconductor chip appears to be defective when in fact the chip is still operational.
FIG. 2 illustrates the effect of tightening the test time relative to the machine clock cycle. In this example, TTEST occurs before TMC, thereby making the slack of Path B smaller than the slack of the Path A in relation to the machine cycle time (SSP<SLP). In a non-defective (i.e. good) semiconductor chip, timing defects smaller than SLP do not cause a failure, but since TTEST occurs before a signal traversing along on Path A has settled, the test may indicate that the semiconductor chip is defective. Thus, a good semiconductor chip could be marked as being defective if the captured value is not ignored for the test, resulting in a yield loss because the non-defective chip is incorrectly marked as defective. This yield loss is unavoidable; hence, binning is not an ideal solution for production testing for small delays.
Long path ATPG is another solution for small-delay testing. Long path ATPG requires a guidance mechanism that allows the test generator to make choices which lead to the creation of a test for the transition fault which is exposed by paths with the smallest possible slack. The natural guidance mechanisms are the arrival time and required time values.
SCOAP and Slack Based ATPG
ATPG techniques take a target fault and systematically exhaust the test search space of inputs and scan flip-flops to generate a test pattern for the fault. ATPG starts from the fault site, obtains a difference “D”, between the good machine and faulty machine and drives the difference to an observable point (i.e. a scan flip-flop or an output). During each step of the process, the ATPG tool makes decisions among the many possible choices available during the traversal of the design. Sandia Controllability/Observability Analysis Program (SCOAP) has been the traditional guidance mechanism which guides ATPG to make decisions such that fewer decisions need to be made to create a test for a given fault.
The efficiency of the transition fault model lies in the fact that it assumes a lumped delay at the fault site. Any path which can expose the fault at the fault site, regardless of the slack time for the path, can be used to detect the fault. In contract, the selection of a path with the smallest slack time possible requires the generation of test patterns for the fault site to be tied to an ordered list of patterns that pass through the fault site. The ordered list of paths is ordered from the path with the smallest slack to the path with the largest slack.
Long path ATPG requires a guidance mechanism to help generate a test which exposes the fault along the path with the least slack from the fault site to an observable point (scan flip-flop or output), and from the fault site to an input (or scan flip-flop). If the path with the least slack is not testable the next path with a larger slack is tried. Thus, ATPG needs to be guided by the arrival and required times (generated from static timing analysis) in the forward direction and reverse direction for the fault effects, and by the traditional SCOAP numbers for justification of off-path values where the length of the path is not relevant.
FIGS. 3A and 3B illustrate the results of the arrival time and required time calculations generated from a timing analysis tool. FIGS. 3A and 3B conceptually show arrival time and required time numbers as (−,−) to depict minimum and maximum values, respectively. In a levelized design, the arrival time is computed in a forward pass of the static timing analysis tool. A minimum and maximum arrival time is propagated for every node in the design. In a levelized design, minimum and maximum required times are computed in the reverse direction. The difference between the minimum of the required time and the maximum of the arrival time at any given net is the slack for that net for setup time (i.e. the longest path). The difference between the maximum of the required time and the minimum of the arrival time gives the slack for hold time (i.e. the shortest path).Setup: Slack=RMIN−AMAX Hold: Slack=RMAX−AMIN Arrival Time Inaccuracy
FIG. 4 illustrates a common clock path. The setup time constraint (i.e. the long path) for the capturing flip-flop is computed as a difference between the maximum arrival time from the launch path of the data (max path 402) and the minimum arrival time from the clock path of the capturing flip-flop (min path 404). In other words the required time on the data path comes from the arrival times of the clock path at the capturing flip-flop.
The two paths that are combined to obtain the slack at the capturing flip-flop have common logic in the clock path. For this common logic, a maximum time is considered along one path and the minimum time is considered along the other path. A given path cannot be at its maximum and minimum times simultaneously. The difference between the maximum and minimum values of the delays along the common portion of the clock path leads to pessimism in the slack calculations. While the launching and capturing transitions are not propagated in the same clock period, they are one or at most few clock periods apart. The largest delay variations are not caused by any effects that change within a few clock periods. For the purposes of transition fault testing, the error due to common clock pessimism exists.
FIG. 5 illustrates the effect of clock network pessimism. It contains clock signal 502, a plurality of gates, and flip-flops 1-3. The minimum and maximum delays of the logic are shown in parentheses above each primitive (min, max). The combinational gates have a shortest delay of 1 time unit and a longest delay of 6 time units (1, 6). The FF1 has a clock-to-Q delay of (1, 2), FF2 has a setup constraint of (3, 4). Note that FF3 has a setup constraint of (0, 2). Also note that the nets have no delay (0, 0).
If T is the clock period, the slack time on FF2 without clock network pessimism is T+1+1−(6+6+6+2+4)=T-22 time units. When the overlap of the clock network is considered, (6+6)−(1+1)=10 time units, the slack time is T-12 time units. The timing slack for FF3 without clock network pessimism is T+1−(6+6+6+2+2)=T-21 time units. Clock network pessimism is 6−1=5 time units in this case. With this correction, the slack for FF3 is T-16 time units. Note that the critical path (i.e. the longest path) without any correction for clock network pessimism is from FF1 to FF2. With clock pessimism removed, the critical path is from FF1 to FF3. In deep sub-micron semiconductor processes, the clock networks are longer to accommodate larger chips. Hence, clock network delay plays a significant role in the slack calculations.
FIG. 6 illustrates the impact of common clock path pessimism on the slack computations. This impact is so significant that it cannot be ignored. In fact, common clock path pessimism contributes so much to the slack calculations that arrival time and required time numbers lead to incorrect identification of paths with minimum slack if common clock path pessimism is not taken into account. Unfortunately, present techniques for generating slack times for delay fault testing do not account for common clock path pessimism. Thus, the longest path that exposes a delay fault at the fault site may be incorrectly identified.
Furthermore, the amount of clock path pessimism for a given slack number is path dependent because the common clock network can only be determined once a path is established. Hence, ATPG for small-delay testing needs to try every possible launch-capture scenario for every decision point to determine the slack numbers for a path that exposes the fault and propagates the fault effect to an observable point.
As a result of the above-described problems, present techniques for precise small-delay transition fault testing are not practical. Even if accurate tests for transition faults are generated which exposes a transition fault along the path with the least slack, other faults that are fortuitously detected cannot be dropped during fault simulation. The random nature of fault detection makes the probability very low that a fault which is dropped in non-small-delay transition mode is detected along a path with the least slack. Note that without the use of fault dropping, test pattern inflation and excessive runtimes for test pattern generation results.
Hence, what is needed is a method and an apparatus for generating test patterns for small-delay defect testing of semiconductor chips without the problems described above.